The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same and, more particularly, to technology effective when applied to a semiconductor integrated circuit device having a rewiring including a metal film on the top of a plurality of wiring layers formed over a main surface of a semiconductor substrate and a method of manufacturing the same.
In a, semiconductor integrated circuit device, on the top of a semiconductor substrate on which a semiconductor element, for example, a CMIS (Complementary Metal Insulator Semiconductor) transistor, is formed, a multilayer wiring is formed by a metal film containing, for example, a Cu (copper) or Al (aluminum) alloy as a main component, and a final passivation film is formed on the top of the multilayer wiring.
Here, as disclosed in, for example, Patent Document 1 (Japanese Patent Laid-Open No. 2003-234348), the technology to form a rewiring containing Cu as a main component on a final passivation film and to electrically couple an electrode pad formed in the uppermost wiring layer under the final passivation film and the rewiring is known.